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features description applications ads1000 sbas357 ? september 2006 low power, 12-bit analog-to-digital converter with i 2 c? interface complete 12-bit data acquisition system in the ads1000 is an i 2 c-compatible serial interface a tiny sot-23 package analog-to-digital (a/d) converter with differential inputs and 12 bits of resolution in a tiny sot23-6 low current consumption: only 90 m a package. conversions are performed ratiometrically, integral nonlinearity: 1lsb max using the power supply as the reference voltage. the single-cycle conversion ads1000 operates from a single power supply ranging from 2.7v to 5.5v. programmable gain amplifier gain = 1, 2, 4 or 8 the ads1000 performs conversions at a rate of 128 128sps data rate samples per second (sps). the onboard programmable gain amplifier (pga), which offers i 2 c interface with two available addresses gains of up to 8, allows smaller signals to be power supply: 2.7v to 5.5v measured with high resolution. in single-conversion pin- and software-compatible with 16-bit mode, the ads1000 automatically powers down after ads1100 a conversion, greatly reducing current consumption during idle periods. the ads1000 is designed for applications where voltage monitors space and power consumption are major considerations. typical applications include portable battery management instrumentation, consumer goods, and voltage industrial process control monitoring. consumer goods temperature measurement please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. i2c is a trademark of royal philips electronics b.v., the netherlands. all other trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2006, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. bd0
ads1000 clock oscillator i c interface 2 a/d converter pga a = 1, 2, 4, or 8 v dd v in+ v in - gnd sda scl
package/ordering information absolute maximum ratings (1) ads1000 sbas357 ? september 2006 this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. for the most current package and ordering information, see the package option addendum located at the end of this datasheet or see the ti website at www.ti.com . over operating free-air temperature range (unless otherwise noted) ads1000 unit v dd to gnd ?0.3 to +6 v input current (momentary) 100 ma input current (continuous) 10 ma voltage to gnd, v in+ , v in? ?0.3 to v dd to +0.3 v voltage to gnd, sda, scl ?0.5 to +6 v maximum junction temperature, t j +150 c operating temperature ?40 to +125 c storage temperature ?60 to +150 c lead temperature (soldering, 10s) +300 c (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods may affect device reliability. pin configuration 2 www .ti.com note: marking text direction indicates pin 1. marking text depends on i c address; see package option addendum. 2 bd0 v in - 6 v dd 5 sda 4 scl 3 gnd 2 v in+ 1 bd1 v in - 6 v dd 5 sda 4 scl 3 gnd 2 v in+ 1 i c address: 1001000 2 i c address: 1001001 2
electrical characteristics ads1000 sbas357 ? september 2006 all specifications at ?40 c to +85 c, v dd = 5v, gnd = 0v, and all pgas, unless otherwise noted. ads1000 parameter conditions min typ max unit analog input full-scale input voltage (v in+ ) ? (v in? ) v dd /pga (1) v analog input voltage v in+ , v in? to gnd gnd ? 0.2 v dd + 0.2 v differential input impedance 2.4/pga m w common-mode input impedance 8 m w system performance resolution no missing codes 12 bits data rate 104 128 184 sps integral nonlinearity (inl) 0.1 1 lsb offset error 1 2 lsb gain error 0.01 0.1 % digital input/output logic level v ih 0.7 gnd 6 v v il gnd ? 0.5 0.3 v dd v v ol i ol = 3ma gnd 0.4 v input leakage i ih v ih = 5.5v 10 m a i il v il = gnd ? 10 m a power-supply requirements power-supply voltage v dd 2.7 5.5 v supply current power-down 0.05 2 m a active 90 150 m a power dissipation m a v dd = 5.0v 450 750 m w v dd = 3.0v 210 m w (1) each input, v in+ and v in? , must meet the absolute input voltage specifications. 3 www .ti.com
typical characteristics ads1000 sbas357 ? september 2006 at t a = 25 c and v dd = 5v, unless otherwise indicated. supply current vs temperature supply current vs i 2 c bus frequency figure 1. figure 2. offset error vs temperature gain error vs temperature figure 3. figure 4. data rate vs temperature figure 5. 4 www .ti.com 250 225 200 175 150 125 100 75 50 10 100 1k 10k i 2 c bus frequency (khz) i vdd ( m a) 25 c - 40 c 125 c 120 100 80 60 40 i vdd ( m a) - 60 - 40 - 20 0 20 40 60 80 100 120 140 temperature ( c) v dd = 5v v dd = 2.7v pga = 8 pga = 4 pga = 2 pga = 1 2.01.0 0.0 1.0 2.0 -- - 40 - 20 0 20 40 60 80 100 120 140 - 60 temperature ( c) offset error (mv) pga = 8 pga = 4 pga = 1 pga = 2 0.040.03 0.02 0.01 0.00 0.01 0.02 0.03 0.04 -- - - - 40 - 20 0 20 40 60 80 100 120 140 - 60 temperature ( c) gain error (%) v dd = 2.7v v dd = 5v 160 144 128 112 96 data rate (sps) - 60 - 40 - 20 0 20 40 60 80 100 120 140 temperature ( c)
analog-to-digital converter reset and power-up output code calculation i 2 c interface clock generator using the ads1000 operating modes ads1000 sbas357 ? september 2006 theory of operation places the result in the output register, and the ads1000 is a fully differential, 12-bit a/d immediately begins another conversion. when the converter. the ads1000 allows users to obtain ads1000 is in continuous conversion mode, the precise measurements with a minimum of effort, and st/bsy bit in the configuration register always reads the device is extremely easy to design with and '1'. configure. in single conversion mode, the ads1000 waits until the ads1000 consists of an a/d converter core with the st/bsy bit in the conversion register is set to '1'. adjustable gain, a clock generator, and an i 2 c when this happens, the ads1000 powers up and interface. each of these blocks are described in performs a single conversion. after the conversion detail in the sections that follow. completes, the ads1000 places the result in the output register, resets the st/bsy bit to '0' and powers down. writing a '1' to st/bsy while a conversion is in progress has no effect. the ads1000 uses a switched-capacitor input stage. to external circuitry, it looks roughly like a when switching from continuous conversion mode to resistance. the resistance value depends on the single conversion mode, the ads1000 will complete capacitor values and the rate at which they are the current conversion, reset the st/bsy bit to '0' switched. the switching clock is generated by the and power-down the device. onboard clock generator, so its frequency, nominally 275khz, is dependent on supply voltage and temperature. the capacitor values depend on the when the ads1000 powers up, it automatically pga setting. performs a reset. as part of the reset, the ads1000 the common-mode and differential input impedances sets all of the bits in the configuration register to their are different. for a gain setting of pga, the respective default settings. differential input impedance is typically 2.4m w /pga. the ads1000 responds to the i 2 c general call the common-mode impedance is typically 8m w . reset command. when the ads1000 receives a general call reset, it performs an internal reset, exactly as though it had just been powered on. the ads1000 outputs codes in binary two?s complement format. the output code is confined to the range of numbers: ?2048 to 2047, and is given the ads1000 communicates through an i 2 c by: (inter-integrated circuit) interface. the i 2 c interface is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. devices on the i 2 c bus only drive the bus lines low, by connecting them to ground; they never drive the bus lines high. instead, the bus wires are pulled high by pull-up resistors, so the bus wires are high when the ads1000 features an onboard clock generator. no device is driving them low. this way, two devices the typical characteristics show variations in data cannot conflict; if two devices drive the bus rate over supply voltage and temperature. it is not simultaneously, there is no driver contention. possible to operate the ads1000 with an external clock. communication on the i 2 c bus always takes place between two devices, one acting as the master and the other acting as the slave. both masters and slaves can read and write, but slaves can only do so under the direction of the master. some i 2 c devices can act as masters or slaves, but the ads1000 can the ads1000 operates in one of two modes: only act as a slave device. continuous conversion and single conversion. in continuous conversion mode, the ads1000 continuously performs conversions. once a conversion has been completed, the ads1000 5 www .ti.com output code 2048(pga) v in v in ? v dd
ads1000 sbas357 ? september 2006 an i 2 c bus consists of two lines, sda and scl. sda 10-bit addresses; see the i 2 c specification for carries data; scl provides the clock. all data is details.) the master sends an address in the transmitted across the i 2 c bus in groups of eight bits. address byte, together with a bit that indicates to send a bit on the i 2 c bus, the sda line is driven whether it wishes to read from or write to the slave to the bit level while scl is low (a low on sda device. indicates the bit is '0'; a high indicates the bit is '1'). every byte transmitted on the i 2 c bus, whether it be once the sda line has settled, the scl line is address or data, is acknowledged with an brought high, then low. this pulse on scl clocks the acknowledge bit. when a master has finished sda bit into the receiver shift register. sending a byte, eight data bits, to a slave, it stops the i 2 c bus is bidirectional: the sda line is used driving sda and waits for the slave to acknowledge both for transmitting and receiving data. when a the byte. the slave acknowledges the byte by pulling master reads from a slave, the slave drives the data sda low. the master then sends a clock pulse to line; when a master sends to a slave, the master clock the acknowledge bit. similarly, when a master drives the data line. the master always drives the has finished reading a byte, it pulls sda low to clock line. the ads1000 never drives scl, because acknowledge to the slave that it has finished reading it cannot act as a master. on the ads1000, scl is the byte. it then sends a clock pulse to clock the bit. an input only. (remember that the master always drives the clock line.) most of the time the bus is idle, no communication takes place, and both lines are high. when a not-acknowledge is performed by simply leaving communication takes place, the bus is active. only sda high during an acknowledge cycle. if a device is master devices can start a communication. they do not present on the bus, and the master attempts to this by causing a start condition on the bus. address it, it will receive a not-acknowledge because normally, the data line is only allowed to change no device is present at that address to pull the line state while the clock line is low. if the data line low. changes state while the clock line is high, it is either when a master has finished communicating with a a start condition or its counterpart, a stop condition. slave, it may issue a stop condition. when a stop a start condition is when the clock line is high and condition is issued, the bus becomes idle again. a the data line goes from high to low. a stop condition master may also issue another start condition. when is when the clock line is high and the data line goes a start condition is issued while the bus is active, it is from low to high. called a repeated start condition. after the master issues a start condition, it sends a a timing diagram for an ads1000 i 2 c transaction is byte that indicates with which slave device it wants to shown in figure 6 . table 1 gives the parameters for communicate. this byte is called the address byte. this diagram. each device on an i 2 c bus has a unique 7-bit address to which it responds. (slaves can also have 6 www .ti.com
ads1000 sbas357 ? september 2006 figure 6. i 2 c timing diagram table 1. timing diagram definitions fast mode high-speed mode parameter min max min max units sclk operating frequency f (sclk) 0.4 3.4 mhz bus free time between stop and start t (buf) 600 160 ns condition hold time after repeated start condition. t (hdsta) 600 160 ns after this period, the first clock is generated. repeated start condition setup time t (susta) 600 160 ns stop condition setup time t (susto) 600 160 ns data hold time t (hddat) 0 0 ns data setup time t (sudat) 100 10 ns sclk clock low period t (low) 1300 160 ns sclk clock high period t (high) 600 60 ns clock/data fall time t f 300 160 ns clock/data rise time t r 300 160 ns 7 www .ti.com t (buf) t (hdsta) t (low) t r t f t (hddat) t (high) t (susta) t (sudat) t (hdsta) t (susto) scl sda p s s p
i 2 c general call registers output register i 2 c data rates ads1000 sbas357 ? september 2006 ads1000 in standard or fast modes, but high-speed mode must be activated. to activate ads1000 i 2 c addresses high-speed mode, send a special address byte of the ads1000 i 2 c address is either 1001000 or 00001xxx following the start condition, where the 1001001, set at the factory. the address is identified xxx bits are unique to the hs-capable master. this with an a0 or an a1 within the orderable name. byte is called the hs master code. (note that this is different from normal address bytes; the low bit does the two different i 2 c variants are also marked not indicate read/write status.) the ads1000 will not differently. devices with an i 2 c address of 1001000 acknowledge this byte; the i 2 c specification prohibits have packages marked bd0, while devices with an acknowledgment of the hs master code. on i 2 c address of 1001001 are marked with bd1. see receiving a master code, the ads1000 will switch on the package/ordering information table for a its high-speed mode filters, and will communicate at complete listing of the ads1000 i 2 c addresses and up to 3.4mhz. the ads1000 switches out of hs tape and reel size. mode with the next stop condition. for more information on high-speed mode, consult the i 2 c specification. the ads1000 responds to general call reset, which is an address byte of 00h followed by a data byte of 06h. the ads1000 acknowledges both bytes. the ads1000 has two registers that are accessible on receiving a general call reset, the ads1000 via its i 2 c port. the output register contains the performs a full internal reset, just as though it had result of the last conversion; the configuration been powered off and then on. if a conversion is in register allows users to change the ads1000 process, it is interrupted; the output register is set to operating mode and query the status of the device. zero, and the configuration register returns to its default setting. the ads1000 always acknowledges the general the 16-bit output register contains the result of the call address byte of 00h, but it does not last conversion in binary two?s complement format. acknowledge any general call data bytes other than since the port yields 12 bits of data, the ads1000 04h or 06h. outputs right-justified and sign-extended codes. this output format makes it possible to perform averaging using a 16-bit accumulator. the i 2 c bus operates in one of three speed modes: following reset or power-up, the output register is standard, which allows a clock frequency of up to cleared to '0'; it remains zero until the first conversion 100khz; fast, which allows a clock frequency of up is completed. therefore, if a user reads the to 400khz; and high-speed mode (also called hs ads1000 just after reset or power-up, the output mode), which allows a clock frequency of up to register will read '0'. 3.4mhz. the ads1000 is fully compatible with all three modes. the output register format is shown in table 2 . no special action needs to be taken to use the table 2. output register bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name d15 (1) d14 (1) d13 (1) d12 (1) d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (1) d15?d12 are sign extensions of 12-bit data. 8 www .ti.com
configuration register reading from the ads1000 writing to the ads1000 ads1000 sbas357 ? september 2006 bits 1 - 0: pga a user controls the ads1000 operating mode and bits 1 and 0 control the ads1000 gain setting; see pga settings via the 8-bit configuration register. the table 4 . configuration register format is shown in table 3 . the default setting is 80h. table 4. pga bits pga1 pga0 gain table 3. configuration register 0 (1) 0 (1) 1 (1) 7 6 5 4 3 2 1 0 0 1 2 st/bsy 0 0 sc 0 0 pga1 pga0 1 0 4 1 1 8 bit 7: st/bsy (1) default setting. the meaning of the st/bsy bit depends on whether it is being written to or read from. in single conversion mode, writing a '1' to the st/bsy bit causes a conversion to start, and writing a user can read the output register and the contents a '0' has no effect. in continuous conversion mode, of the configuration register from the ads1000. to the ads1000 ignores the value written to st/bsy. do this, address the ads1000 for reading, and read when read in single conversion mode, st/bsy three bytes from the device. the first two bytes are indicates whether the a/d converter is busy taking a the output register contents; the third byte is the conversion. if st/bsy is read as '1', the a/d configuration register contents. converter is busy, and a conversion is taking place; if a user does not always have to read three bytes '0', no conversion is taking place, and the result of from the ads1000. if only the contents of the output the last conversion is available in the output register. register are needed, read only two bytes. in continuous mode, st/bsy is always read as '1'. reading more than three bytes from the ads1000 bits 6 - 5: reserved has no effect. all of the bytes beginning with the fourth byte will be ffh. see figure 7 for a timing bits 6 and 5 must be set to zero. diagram of an ads1000 read operation. bit 4: sc sc controls whether the ads1000 is in continuous conversion or single conversion mode. when sc is a user can write new contents into the configuration '1', the ads1000 is in single conversion mode; when register (the contents of the output register cannot sc is '0', the ads1000 is in continuous conversion change). to do this, address the ads1000 for mode. the default setting is '0'. writing, and write one byte to it. this byte is written into the configuration register. bits 3 - 2: reserved writing more than one byte to the ads1000 has no bits 3 and 2 must be set to zero. effect. the ads1000 ignores any bytes sent to it after the first one, and will only acknowledge the first byte. see figure 8 for a timing diagram of an ads1000 write operation. 9 www .ti.com
ads1000 sbas357 ? september 2006 figure 7. timing diagram for reading from the ads1000 figure 8. timing diagram for writing to the ads1000 10 www .ti.com frame 1: i c slave address byte 2 frame 2: output register upper byte start by master ack by ads1000 ack by master from ads1000 from ads1000 1 9 1 9 sda scl sda (continued) scl (continued) 1 0 0 1 a2 a1 a0 r/w d15 d14 d13 d12 d11 d10 d9 d8 frame 3: output register lower byte frame 4: configuration register (optional) ack by master stop by master ack by master from ads1000 1 9 1 d7 d6 d5 d4 d3 d2 d1 d0 st/ bsy 0 0 sc 0 0 pga1 pga0 9 frame 1: i c slave address byte 2 frame 2: configuration register 1 start by master ack by ads1000 ack by ads1000 1 9 1 9 sda scl 0 0 1 a2 a1 a0 r/w st/ bsy 0 0 sc pga1 pga0 stop by master 0 0
application information basic connections ads1000 sbas357 ? september 2006 the ads1000 interfaces directly to standard mode, fast mode, and high-speed mode i 2 c controllers. any microcontroller i 2 c peripheral, including master-only for many applications, connecting the ads1000 is and non-multiple-master i 2 c peripherals, will work extremely simple. a basic connection diagram for the with the ads1000. the ads1000 does not perform ads1000 is shown in figure 9 . clock-stretching (that is, it never pulls the clock line the fully differential voltage input of the ads1000 is low), so it is not necessary to provide for this unless ideal for connection to differential sources with other devices are on the same i 2 c bus. moderately low source impedance, such as bridge pull-up resistors are necessary on both the sda and sensors and thermistors. although the ads1000 can scl lines because i 2 c bus drivers are open-drain. read bipolar differential signals, it cannot accept the size of these resistors depends on the bus negative voltages on either input. it may be helpful to operating speed and capacitance of the bus lines. think of the ads1000 positive voltage input as higher-value resistors consume less power, but noninverting, and of the negative input as inverting. increase the transition times on the bus, limiting the when the ads1000 is converting, it draws current in bus speed. lower-value resistors allow higher speed short spikes. the 0.1 m f bypass capacitor supplies at the expense of higher power consumption. long the momentary bursts of extra current needed from bus lines have higher capacitance and require the supply. smaller pullup resistors to compensate. the resistors should not be too small; if they are, the bus drivers may not be able to pull the bus lines low. figure 9. typical connections of the ads1000 11 www .ti.com 12 3 65 4 v in - v in+ scl gnd v dd sda ads1000 positive input (0v to 5v) negative input (0v to 5v) v dd v dd 4.7 f (typ.) m microcontroller or microprocessor with i c port 2 scl sda i c pull-up resistors 1k to 10k (typ.) w w 2
connecting multiple devices using gpio ports for i 2 c single-ended inputs ads1000 sbas357 ? september 2006 connecting two ads1000s to a single bus is almost trivial. an example showing two ads1000s and one ads1100 connected on a single bus is shown in figure 10 . multiple devices can be connected to a single bus (provided that their addresses are different). note that only one set of pull-up resistors is needed per bus. a user might find that he or she needs to lower the pull-up resistor values slightly to compensate for the additional bus capacitance presented by multiple devices and increased line length. figure 11. using gpio with a single ads1000 bit-banging i 2 c with gpio pins can be done by setting the gpio line to zero and toggling it between input and output modes to apply the proper bus states. to drive the line low, the pin is set to output a '0'; to let the line go high, the pin is set to input. when the pin is set to input, the state of the pin can be read; if another device is pulling the line low, this device will read as a '0' in the port input register. note that no pull-up resistor is shown on the scl line. in this simple case, the resistor is not needed; the microcontroller can simply leave the line on output, and set it to '1' or '0' as appropriate. it can do this because the ads1000 never drives its clock line low. this technique can also be used with multiple devices, and has the advantage of lower current consumption resulting from the absence of a resistive pull-up. if there are any devices on the bus that may drive their clock lines low, the above method should not be used; the scl line should be high-z or zero and a pull-up resistor provided as usual. note also that this cannot be done on the sda line in any case, because the ads1000 does drive the sda line low figure 10. connecting multiple ads1000s from time to time, as all i 2 c devices do. some microcontrollers have selectable strong pull-up circuits built into the gpio ports. in some cases, most microcontrollers have programmable these can be switched on and used in place of an input/output pins that can be set in software to act as external pull-up resistor. weak pull-ups are also inputs or outputs. if an i 2 c controller is not available, provided on some microcontrollers, but usually these the ads1000 can be connected to gpio pins, and are too weak for i 2 c communication. if there is any the i 2 c bus protocol simulated, or bit-banged, in doubt about the matter, test the circuit before software. an example of this for a single ads1000 is committing it to production. shown in figure 11 . although the ads1000 has a fully differential input, it can easily measure single-ended signals. a simple single-ended connection scheme is shown in figure 12 . the ads1000 is configured for single-ended measurement by grounding either of its 12 www .ti.com 12 3 65 4 v in - v in+ scl gnd v dd sda ads1000 v dd microcontroller or microprocessor with i c port 2 scl sda note: ads1000 powerand input connections omitted for clarity. 12 3 65 4 sda scl i c pull-up resistors 1k to 10k (typ.) w w 2 v dd microcontroller or microprocessor with i c port 2 v in - v in+ scl gnd v dd sda ads1000a0 12 3 65 4 v in - v in+ scl gnd v dd sda ads1000a1 12 3 65 4 v in - v in+ scl gnd v dd sda ads1100a2 note: ads1000 powerand input connections omitted for clarity.
low-side current monitor ads1000 sbas357 ? september 2006 input pins, usually v in? , and applying the input signal to v in+ . the single-ended signal can range from figure 13 shows a circuit for a low-side shunt-type ?0.2v to v dd + 0.3v. the ads1000 loses no linearity current monitor. the circuit reads the voltage across anywhere in its input range. negative voltages a shunt resistor, which is sized as small as possible cannot be applied to this circuit because the while still giving a readable output voltage. this ads1000 inputs can only accept positive voltages. voltage is amplified by an opa335 low-drift op-amp, and the result is read by the ads1000. figure 12. measuring single-ended inputs the ads1000 input range is bipolar differential with respect to the reference, that is, v dd . the single-ended circuit shown in figure 12 covers only figure 13. low-side current measurement half the ads1000 input scale because it does not produce differentially negative inputs; therefore, one it is recommended that the ads1000 be operated at bit of resolution is lost. the drv134 balanced line a gain of 8. the gain of the opa335 can then be set driver can be employed to regain this bit for lower. for a gain of 8, the op amp should be single-ended signals. configured to give a maximum output voltage of no greater than 0.75v. if the shunt resistor is sized to negative input voltages must be level-shifted. a good provide a maximum voltage drop of 50mv at candidate for this function is the ths4130 differential full-scale current, the full-scale input to the ads1000 amplifier, which can output fully differential signals. is 0.63v. this device can also help recover the lost bit noted previously for single-ended positive signals. level-shifting can also be performed using the drv134. 13 12 3 65 4 v in - v in+ scl gnd v dd sda ads1000 v dd outputcodes 0 2048 - filter capacitor 33pf to 100pf (typ.) 0v v single-ended - dd www .ti.com notes: (1) pull-down resistor to allow accurate swing to 0v. (2) r is sized for a 50mv drop at full-scale current. s v load r s (2) 1k w g = 12.5 - 5v opa335 r49.9k 3 w (1) fs = 0.63v 5v 5v 11.5k w ads1000 i c 2 (pga gain = 8) 5v fs
additional recommendations ads1000 sbas357 ? september 2006 stabilized; this momentary spike can damage the ads1000. sometimes this damage is incremental the ads1000 is fabricated in a small-geometry and results in slow, long-term failure?which can be low-voltage process. the analog inputs feature distastrous for permanently installed, low- protection diodes to the supply rails. however, the maintenance systems. current-handling ability of these diodes is limited, and the ads1000 can be permanently damaged by if using an op amp or other front-end circuitry with analog input voltages that remain more than the ads1000, be sure to take the performance approximately 300mv beyond the rails for extended characteristics of this circuitry into account; a chain is periods. one way to protect against overvoltage is to only as strong as its weakest link. place current-limiting resistors on the input lines. the any data converter is only as good as its reference. ads1000 analog inputs can withstand momentary for the ads1000, the reference is the power supply, currents of as large as 10ma. and the power supply must be clean enough to the previous paragraph does not apply to the i 2 c achieve the desired performance. if a power-supply ports, which can both be driven to 6v regardless of filter capacitor is used, it should be placed close to the supply. the v dd pin, with no vias placed between the capacitor and the pin. the trace leading to the pin if the ads1000 is driven by an op amp with high should be as wide as possible, even if it must be voltage supplies, such as 12v, protection should be necked down at the device. provided, even if the op amp is configured so that it will not output out-of-range voltages. many op amps seek to one of the supply rails immediately when power is applied, usually before the input has 14 www .ti.com
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) ads1000a0idbvr active sot-23 dbv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim ADS1000A0IDBVRG4 active sot-23 dbv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim ads1000a0idbvt active sot-23 dbv 6 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim ads1000a0idbvtg4 active sot-23 dbv 6 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim ads1000a1idbvr active sot-23 dbv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim ads1000a1idbvrg4 active sot-23 dbv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim ads1000a1idbvt active sot-23 dbv 6 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim ads1000a1idbvtg4 active sot-23 dbv 6 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 2-oct-2006 addendum-page 1

important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security low power wireless www.ti.com/lpw telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2006, texas instruments incorporated

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